H5AN8G8NCJR-VKC SK hynix 8Gb DDR4 SDRAM
SK hynix H5AN8G8NCJR-VKC is an 8Gb x8 DDR4 SDRAM component. This component provides a synchronous external-memory interface. The controller configuration and board connections must match the complete ordering code.
Availability, quantity and lead time are confirmed in your quotation.
H5AN8G8NCJR-VKC Specifications
Basic specifications
- Manufacturer
- SK hynix
- Complete part number
- H5AN8G8NCJR-VKC
- Memory type
- DDR4 SDRAM
- Component density
- 8Gb
- Organization
- 1G x8
- Data bus width
- x8
Speed & electrical
- Data rate
- 2666 MT/s
- Clock
- 1333 MHzCK frequency; half the stated transfer rate.
- Native CL / tRCD / tRP
- 19-19-19Operating-mode conditions below.
- VDD / VDDQ
- 1.2 V
- VDD / VDDQ operating range
- 1.14–1.26 V
- VPP
- 2.5 VOperating range: 2.375–2.750 V.
Package & temperature
- Package
- 78-ball FBGA
- Temperature option
- Commercial (C)
- Body size
- 7.50 ±0.10 × 11.00 ±0.10 mmW × L; drawing tolerances.
- Package height
- 1.10 ±0.10 mm
- Ball pitch
- 0.80 mm
- Normal case range
- 0 to +85 °CCase surface at top center of package.
- Extended case range
- >85 to +95 °CAdditional refresh and self-refresh conditions apply.
Technical notes & sources
Native timing. At DDR4-2666: 0.750 ≤ tCK < 0.833 ns; CL19 and CWL 14 or 18. tAA is 14.25–18 ns; tRCD and tRP are at least 14.25 ns; tRAS is at least 32 ns and at most 9 × tREFI. tRC is at least 46.25 ns. DLL must be enabled and gear-down disabled. Read DBI uses CL22 and adds 3nCK to the tAA limits. Use only supported CL/CWL combinations and retain the listed conditions for optional down-binning.
Supply conditions. VDDQ must not exceed VDD and must track it; AC parameters are characterized with both rails tied together. The DC-condition bandwidth is limited to 20 MHz. Keep VDD and VDDQ within 300 mV, VREFCA at or below 0.6 × VDDQ (at or below 300 mV while both rails are below 500 mV), and VPP at or above VDD/VDDQ. Absolute-maximum ratings do not define normal operation.
Temperature and refresh. The case temperature is measured at the top center of the package. Above 85 °C and up to 95 °C, double the refresh-command frequency, reducing tREFI to 3.9 µs. For self refresh in this range, use the documented manual extended setting MR2[A7:A6]=10. The temperature grade does not configure the controller automatically.
Manufacturer declaration: SK hynix describes this documented device family as lead-free, halogen-free and RoHS compliant. This manufacturer statement does not certify an offered lot or establish a separate REACH declaration.
Manufacturer sources: SK hynix 8Gb CJR DDR4 Datasheet
H5AN8G8NCJR-VKC Datasheet
Specification review: 2026-11-09.
Manufacturer package drawing; not a photograph of an offered lot. Manufacturer drawing, not a product photo.
Selection notes
Can a VK part be substituted into an XN operating profile?
Recheck the controller clock and timings before accepting the substitution. VK and XN are different speed bins in the CJR ordering table; the same die and capacity do not qualify a VK device for an XN operating point. Keep the complete VKC suffix on the RFQ and BOM.
Is a slower clock enough to approve a different CL/CWL pair?
Use the supported combinations and clock-period bounds in the VK table. Optional down-bin settings require their stated support, and reserved combinations remain unavailable even when the controller can program them.
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