H5AN8G6NDJR-XNC SK hynix 8Gb DDR4 SDRAM
SK hynix H5AN8G6NDJR-XNC is an 8Gb x16 DDR4 SDRAM component. This component provides a synchronous external-memory interface. The controller configuration and board connections must match the complete ordering code.
Availability, quantity and lead time are confirmed in your quotation.
H5AN8G6NDJR-XNC Specifications
Basic specifications
- Manufacturer
- SK hynix
- Complete part number
- H5AN8G6NDJR-XNC
- Memory type
- DDR4 SDRAM
- Component density
- 8Gb
- Organization
- 512M x16
- Data bus width
- x16
Speed & electrical
- Data rate
- 3200 MT/s
- Clock
- 1600 MHzCK frequency; half the stated transfer rate.
- Native CL / tRCD / tRP
- 22-22-22Operating-mode conditions below.
- VDD / VDDQ
- 1.2 V
- VDD / VDDQ operating range
- 1.14–1.26 V
- VPP
- 2.5 VOperating range: 2.375–2.750 V.
Package & temperature
- Package
- 96-ball FBGA
- Temperature option
- Commercial (C)
- Body size
- 7.50 ±0.10 × 13.00 ±0.10 mmW × L; drawing tolerances.
- Ball pitch
- 0.80 mm
- Normal case range
- 0 to +85 °CCase surface at top center of package.
- Extended case range
- >85 to +95 °CAdditional refresh and self-refresh conditions apply.
Technical notes & sources
Native timing. At DDR4-3200: 0.625 ≤ tCK < 0.750 ns; CL22 and CWL 16 or 20. tAA is 13.75–18 ns; tRCD and tRP are at least 13.75 ns; tRAS is at least 32 ns and at most 9 × tREFI. tRC is at least 45.75 ns. DLL must be enabled and gear-down disabled. Use only supported CL/CWL combinations and retain the listed conditions for optional down-binning.
Supply conditions. VDDQ must not exceed VDD and must track it; AC parameters are characterized with both rails tied together. The DC-condition bandwidth is limited to 20 MHz. Keep VDD and VDDQ within 300 mV, VREFCA at or below 0.6 × VDDQ (at or below 300 mV while both rails are below 500 mV), and VPP at or above VDD/VDDQ. Absolute-maximum ratings do not define normal operation.
Temperature and refresh. The case temperature is measured at the top center of the package. Above 85 °C and up to 95 °C, double the refresh-command frequency, reducing tREFI to 3.9 µs. For self refresh in this range, use the documented manual extended setting MR2[A7:A6]=10. The temperature grade does not configure the controller automatically.
Manufacturer declaration: SK hynix describes this documented device family as lead-free, halogen-free and RoHS compliant. This manufacturer statement does not certify an offered lot or establish a separate REACH declaration.
Manufacturer sources: SK hynix 8Gb DJR DDR4 Datasheet

H5AN8G6NDJR-XNC Datasheet
Specification review: 2026-11-09.
Manufacturer package drawing; not a photograph of an offered lot. Manufacturer drawing, not a product photo.
Selection notes
Which specification revision should accompany a DJR substitution?
Keep the revision with the engineering approval. DJR Rev. 1.3 corrected tRC, and Rev. 1.4 retains that correction; compare the offered part against the corrected timing table before carrying over a profile prepared from an older document.
Is the shared 96-ball outline enough for mechanical approval?
Check the offered package drawing and assembly height clearance separately. A matching outline and ball count do not establish every mechanical limit, and the DJR drawing should not inherit the height stated for an AFR or CJR package.
What must the controller do above 85 °C?
Account for the doubled refresh-command frequency and the documented manual extended self-refresh setting. Validate the change into and out of sleep under the hot condition; normal refresh settings alone do not cover the extended case-temperature range.
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