H5AN8G6NCJR-XNC SK hynix 8Gb DDR4 SDRAM
SK hynix H5AN8G6NCJR-XNC is an 8Gb x16 DDR4 SDRAM component. This component provides a synchronous external-memory interface. The controller configuration and board connections must match the complete ordering code.
Availability, quantity and lead time are confirmed in your quotation.
H5AN8G6NCJR-XNC Specifications
Basic specifications
- Manufacturer
- SK hynix
- Complete part number
- H5AN8G6NCJR-XNC
- Memory type
- DDR4 SDRAM
- Component density
- 8Gb
- Organization
- 512M x16
- Data bus width
- x16
Speed & electrical
- Data rate
- 3200 MT/s
- Clock
- 1600 MHzCK frequency; half the stated transfer rate.
- Native CL / tRCD / tRP
- 22-22-22Operating-mode conditions below.
- VDD / VDDQ
- 1.2 V
- VDD / VDDQ operating range
- 1.14–1.26 V
- VPP
- 2.5 VOperating range: 2.375–2.750 V.
Package & temperature
- Package
- 96-ball FBGA
- Temperature option
- Commercial (C)
- Body size
- 7.50 ±0.10 × 13.00 ±0.10 mmW × L; drawing tolerances.
- Package height
- 1.10 ±0.10 mm
- Ball pitch
- 0.80 mm
- Normal case range
- 0 to +85 °CCase surface at top center of package.
- Extended case range
- >85 to +95 °CAdditional refresh and self-refresh conditions apply.
Technical notes & sources
Native timing. At DDR4-3200: 0.625 ≤ tCK < 0.750 ns; CL22 and CWL 16 or 20. tAA is 13.75–18 ns; tRCD and tRP are at least 13.75 ns; tRAS is at least 32 ns and at most 9 × tREFI. Confirm the CJR ACT-to-ACT time before qualifying the controller profile. DLL must be enabled and gear-down disabled. Use only supported CL/CWL combinations and retain the listed conditions for optional down-binning.
Supply conditions. VDDQ must not exceed VDD and must track it; AC parameters are characterized with both rails tied together. The DC-condition bandwidth is limited to 20 MHz. Keep VDD and VDDQ within 300 mV, VREFCA at or below 0.6 × VDDQ (at or below 300 mV while both rails are below 500 mV), and VPP at or above VDD/VDDQ. Absolute-maximum ratings do not define normal operation.
Temperature and refresh. The case temperature is measured at the top center of the package. Above 85 °C and up to 95 °C, double the refresh-command frequency, reducing tREFI to 3.9 µs. For self refresh in this range, use the documented manual extended setting MR2[A7:A6]=10. The temperature grade does not configure the controller automatically.
Manufacturer declaration: SK hynix describes this documented device family as lead-free, halogen-free and RoHS compliant. This manufacturer statement does not certify an offered lot or establish a separate REACH declaration.
Manufacturer sources: SK hynix 8Gb CJR DDR4 Datasheet
H5AN8G6NCJR-XNC Datasheet
Specification review: 2026-11-09.
Manufacturer package drawing; not a photograph of an offered lot. Manufacturer drawing, not a product photo.
Selection notes
Can a DJR timing profile be used for this CJR ordering code?
Keep the profile tied to the qualified die revision. Matching XN speed and x16 organization does not transfer a DJR timing correction to CJR. Check the CJR ACT-to-ACT timing requirement with the controller qualification before accepting a die revision change.
Does the commercial grade allow normal refresh at 95 °C?
Use the hot-temperature refresh conditions when the case exceeds 85 °C, including the documented manual extended setting for self refresh. Evaluate the bandwidth cost and sleep transitions at the actual thermal limit rather than treating the temperature label as permission to retain the normal refresh schedule.
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