H5AN4G6NAFR-UHC SK hynix 4Gb DDR4 SDRAM
SK hynix H5AN4G6NAFR-UHC is a 4Gb x16 DDR4 SDRAM component. This component provides a synchronous external-memory interface. The controller configuration and board connections must match the complete ordering code.
Availability, quantity and lead time are confirmed in your quotation.
H5AN4G6NAFR-UHC Specifications
Basic specifications
- Manufacturer
- SK hynix
- Complete part number
- H5AN4G6NAFR-UHC
- Memory type
- DDR4 SDRAM
- Component density
- 4Gb
- Organization
- 256M x16
- Data bus width
- x16
Speed & electrical
- Data rate
- 2400 MT/s
- Clock
- 1200 MHzCK frequency; half the stated transfer rate.
- Native CL / tRCD / tRP
- 17-17-17Operating-mode conditions below.
- VDD / VDDQ
- 1.2 V
- VDD / VDDQ operating range
- 1.14–1.26 V
- VPP
- 2.5 VOperating range: 2.375–2.750 V.
Package & temperature
- Package
- 96-ball FBGA
- Temperature option
- Commercial (C)
- Body size
- 7.50 ±0.10 × 13.00 ±0.10 mmW × L; drawing tolerances.
- Package height
- 1.10 ±0.10 mm
- Ball pitch
- 0.80 mm
- Normal case range
- 0 to +85 °CCase surface at top center of package.
- Extended case range
- >85 to +95 °CAdditional refresh and self-refresh conditions apply.
Technical notes & sources
Native timing. At DDR4-2400: 0.833 ≤ tCK < 0.937 ns; CL17 and CWL 12 or 16. tAA is 14.16–18 ns; tRCD and tRP are at least 14.16 ns; tRAS is at least 32 ns and at most 9 × tREFI. tRC is at least 46.16 ns. DLL must be enabled and gear-down disabled. Use only supported CL/CWL combinations and retain the listed conditions for optional down-binning.
Supply conditions. VDDQ must not exceed VDD and must track it; AC parameters are characterized with both rails tied together. The DC-condition bandwidth is limited to 20 MHz. Keep VDD and VDDQ within 300 mV, VREFCA at or below 0.6 × VDDQ (at or below 300 mV while both rails are below 500 mV), and VPP at or above VDD/VDDQ. Absolute-maximum ratings do not define normal operation.
Temperature and refresh. The case temperature is measured at the top center of the package. Above 85 °C and up to 95 °C, double the refresh-command frequency, reducing tREFI to 3.9 µs. For self refresh in this range, use the documented manual extended setting MR2[A7:A6]=10. The temperature grade does not configure the controller automatically.
Manufacturer declaration: SK hynix describes this documented device family as lead-free, halogen-free and RoHS compliant. This manufacturer statement does not certify an offered lot or establish a separate REACH declaration.
Manufacturer sources: SK hynix 4Gb AFR DDR4 Datasheet
H5AN4G6NAFR-UHC Datasheet
Specification review: 2026-11-09.
Manufacturer package drawing; not a photograph of an offered lot. Manufacturer drawing, not a product photo.
Selection notes
Can x8 controller settings be reused for this x16 part?
Review the enabled features as well as the bus width. The AFR feature list limits additive latency to x4/x8 and read DBI to x8. Carrying an x8 mode-register configuration into this x16 design can therefore select a feature outside the documented configuration.
What changes when the package runs above 85 °C?
Budget for twice the normal refresh-command frequency and use the documented manual extended-temperature self-refresh setting when sleep is required. Validate active and sleep transitions at the hot condition; a commercial ordering code by itself does not configure either behavior.
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